A Novel Transpose 2T-DRAM based Computing-in-Memory Architecture for On-chip DNN Training and Inference-Reference-Cited by-同舟云学术

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A Novel Transpose 2T-DRAM based Computing-in-Memory Architecture for On-chip DNN Training and Inference

Published:2023-06-11 Issue: Volume: Page:
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Container-title:2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
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Author:

Zhao Yuansheng¹,Shen Zixuan¹,Xu Jiarui¹,Chai Kevin C.T.²,Wu Yanqing³,Wang Chao¹

Affiliation:

1. Huazhong University of Science and Technology,School of Optical and Electronic Information,Wuhan,China

2. Peking University, Beijing,School of Integrated Circuits,Beijing,China

3. Institute of Microelectronics,Agency for Science, Technology and Research,Singapore

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10168547/10168548/10168641.pdf?arnumber=10168641

Reference7 articles.

1. An 800-MHz Mixed- $V_{\text{T}}$ 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

2. 16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing

3. Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

4. In Situ Aging-Aware Error Monitoring Scheme for IMPLY-Based Memristive Computing-in-Memory Systems

5. 15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism;Journal of Low Power Electronics and Applications;2024-01-04

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