Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines

Author:

Filippas Dionysios1,Peltekis Christodoulos1,Dimitrakopoulos Giorgos1,Nicopoulos Chrysostomos2

Affiliation:

1. Democritus University of Thrace,Electrical and Computer Engineering,Greece

2. University of Cyprus,Electrical and Computer Engineering,Cyprus

Publisher

IEEE

Reference31 articles.

1. A survey of quantization methods for efficient neural network inference;gholami,2021

2. Ten lessons from three generations shaped google’s tpuv4i: Industrial product;jouppi;Int Symp Computer Architecture (ISCA),2021

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5. ImageNet Large Scale Visual Recognition Challenge

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2. Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

3. Systolic Array Architecture for Educational Use;2023 27th International Conference on System Theory, Control and Computing (ICSTCC);2023-10-11

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5. The Case for Asymmetric Systolic Array Floorplanning;2023 18th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA);2023-09-28

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