Integrated System-on-Module for Design-Space Exploration of Spiking Neural Networks
Author:
Affiliation:
1. Infineon Technologies AG,Neubiberg,Germany
2. Ferroelectric Memory GmbH,Dresden,Germany
3. Innatera Nanosystems,Rijswijk,The Netherlands
4. University of Erlangen–Nürnberg,Erlangen,Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10168547/10168548/10168582.pdf?arnumber=10168582
Reference37 articles.
1. A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
2. Reliability of analog resistive switching memory for neuromorphic computing
3. Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation
4. Modeling $R{-}2R$ Segmented-Ladder DACs
5. Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Toward Efficient System-on-Module for Design-Space Exploration of Analog Spiking Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08
2. Spiking Neural Networks Design-Space Exploration Platform Supporting Online and Offline Learning;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05
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