Accurate on-chip interconnect evaluation: a time-domain technique-Reference-Cited by-同舟云学术

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Accurate on-chip interconnect evaluation: a time-domain technique

Published:1999-05 Issue:5 Volume:34 Page:623-631
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Soumyanath K.,Borkar S.,Chunyan Zhou ,Bloechel B.A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx4/4/16453/00760372.pdf?arnumber=760372

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis of power supply noise in AMS circuits including the effects of interconnects using estimation by inspection method;AEU - International Journal of Electronics and Communications;2021-09

2. A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis;2009 IEEE Student Conference on Research and Development (SCOReD);2009

3. An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2007-10

4. Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS;2007 IEEE International Electron Devices Meeting;2007

5. Programmable Reference Generator for On-Chip Measurement;2006 NORCHIP;2006-11

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