Analysis of 8-bit Vedic Multiplier using high speed CLA Adder
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9057352/9074834/09074953.pdf?arnumber=9074953
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology;Heliyon;2024-05
2. An Efficient High Performance GDI based 4-bit Vedic Multiplier in 32nm Technology;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01
3. An Efficient Design and Performance Analysis of Novel 8 Bit Modified Wallace Multiplier Using Sklansky Adder in Comparison with Kogge-Stone Adder (KSA);2023 Eighth International Conference on Science Technology Engineering and Mathematics (ICONSTEM);2023-04-06
4. Design and implementation of 8 - bit multiplier using carry adder by comparing with carry look ahead;INTERNATIONAL CONFERENCE ON SCIENCE, ENGINEERING, AND TECHNOLOGY 2022: Conference Proceedings;2023
5. Design of High Speed 8-bit Vedic Multiplier using Brent Kung Adders;2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT);2022-10-03
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