A 10-ps resolution, process-insensitive timing generator IC-Reference-Cited by-同舟云学术

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A 10-ps resolution, process-insensitive timing generator IC

Published:1989-10 Issue:5 Volume:24 Page:1412-1417
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Otsuji T.,Narumi N.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx4/4/1494/00572626.pdf?arnumber=572626

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Accurate and low jitter time-interval generators based on phase shifting method;Review of Scientific Instruments;2012-03

2. FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range;IEEE Transactions on Circuits and Systems I: Regular Papers;2010-06

3. High resolution 20 GHz wideband delay generator;Electronics Letters;2004

4. A simple, precise, and low jitter delay/gate generator;Review of Scientific Instruments;2003-07

5. A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure;IEEE Journal of Solid-State Circuits;1999

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