Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits-Reference-Cited by-同舟云学术

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Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits

Published:1982-04 Issue:2 Volume:17 Page:275-280
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Saraswat K.C.,Mohammadi F.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/22582/01051729.pdf?arnumber=1051729

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