A Review on Emerging Tunnel FET Structures for High-speed and Low-power Circuit Applications
Author:
Affiliation:
1. VIT-AP University,School of Electronics Engineering,Amaravati,AP,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10134754/10134560/10134784.pdf?arnumber=10134784
Reference27 articles.
1. Analysis of Interface Trap Charges on Dielectric Pocket SOI-TFET
2. Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance
3. Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets
4. A Novel Extended Source TFET with δp+- SiGe Layer
5. Source Extended GaSb/GaAs Heterojunction GAATFET to Improve I ON/I OFF Ratio;karthik;2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON),2022
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1. Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability;Physica Scripta;2024-07-02
2. A dielectrically modulated vertical TFET-based biosensor considering irregular probe placement and steric hindrance issues;Micro and Nanostructures;2024-06
3. Performance analysis of highly sensitive vertical tunnel FET for detecting light in near-IR range;Journal of Materials Science: Materials in Electronics;2024-06
4. Performance investigation of elevated source EBG TFET based photosensor for near-infrared light sensing applications;Micro and Nanostructures;2024-04
5. Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects;Physica Scripta;2024-01-04
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