A Review on Emerging Tunnel FET Structures for High-speed and Low-power Circuit Applications

Author:

Pandey Chandan Kumar1,Das Diganta1,Kadava R. N. Karthik1,Ashok Tammisetti1,Anil Kumar P1,Siva RamaKrishna G1

Affiliation:

1. VIT-AP University,School of Electronics Engineering,Amaravati,AP,India

Publisher

IEEE

Reference27 articles.

1. Analysis of Interface Trap Charges on Dielectric Pocket SOI-TFET

2. Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance

3. Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets

4. A Novel Extended Source TFET with δp+- SiGe Layer

5. Source Extended GaSb/GaAs Heterojunction GAATFET to Improve I ON/I OFF Ratio;karthik;2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON),2022

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