FPGA based design of low power reconfigurable router for Network on Chip (NoC)-Reference-Cited by-同舟云学术

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FPGA based design of low power reconfigurable router for Network on Chip (NoC)

Published:2015-05 Issue: Volume: Page:
ISSN:
Container-title:International Conference on Computing, Communication & Automation
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Author:

Bhanwala Amit,Kumar Mayank,Kumar Yogendera

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7126877/7148334/07148581.pdf?arnumber=7148581

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications;Micromachines;2023-10-07

2. Adaptive Routing for Hybrid Photonic–Plasmonic (HyPPI) Interconnection Network for Manycore Processors Using DDDAS on the Chip;Handbook of Dynamic Data Driven Applications Systems;2023

3. Design and Verification of 1X5 ROUTER;2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon);2022-10-16

4. Design of Priority Based Reconfigurable Router in Network on Chip;Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials;2020-01-30

5. S2DIO: an extended scalable 2D mesh network-on-chip routing reconfiguration for efficient bypass of link failures;The Journal of Supercomputing;2019-06-06

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