Author:
Gajski D.D.,Ramachandran L.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software,Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
68 articles.
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1. Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
2. Security of Hardware Generators: Enabling Assurance in High-Level Synthesis;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
3. Acceleration of Trading System Back End with FPGAs Using High-Level Synthesis Flow;Electronics;2023-01-19
4. SecHLS;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16
5. An SMT-Based Reverse Engineering of Register Allocation in High-Level Synthesis;Lecture Notes in Electrical Engineering;2023