A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection
Author:
Affiliation:
1. Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute,Berlin,Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9996588/9996595/09996954.pdf?arnumber=9996954
Reference19 articles.
1. Sparse-YOLO: Hardware/Software Co-Design of an FPGA Accelerator for YOLOv2
2. FCLNN: A Flexible Framework for Fast CNN Prototyping on FPGA with OpenCL and Caffe
3. An FPGA-Based Reconfigurable CNN Accelerator for YOLO
4. A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
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1. Design and Implementation of Nursing-Secure-Care System with mmWave Radar by YOLO-v4 Computing Methods;Applied System Innovation;2024-01-19
2. SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12
3. End-to-end acceleration of the YOLO object detection framework on FPGA-only devices;Neural Computing and Applications;2023-11-13
4. Enhancing FPGA-Based YOLO Object Detection: Multi-Bank Storage Optimization and Model Refinement for Real-Time Applications;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20
5. Dedicated FPGA Implementation of the Gaussian TinyYOLOv3 Accelerator;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10
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