Design Considerations for Sub-90-nm Split-Gate Flash-Memory Cells
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx5/16/4367582/04367612.pdf?arnumber=4367612
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1. Emerging Memory-Based Chip Development for Neuromorphic Computing: Status, Challenges, and Perspectives;IEEE Electron Devices Magazine;2023-09
2. Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology;Solid-State Electronics;2022-08
3. Influence of Common Source and Word Line Electrodes on Program Operation in SuperFlash Memory;Electronics;2021-02-01
4. Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell;Solid-State Electronics;2019-02
5. The modified alpha power law based model of statistical fluctuation in nanometer FGMOSFET;Cogent Engineering;2018-01-01
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