Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology

Author:

Chen Hualun,Xu Zhaozhao,Xiong Wei,Zhang Jian,Xu Xiaojun,Wang Hui,Dang Yang,Wang Jinfeng,Song Wan,Tian Tian,Liu Donghua,Qian Wensheng,Kong Weiran

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference24 articles.

1. A highly reliable 2-bits/cell split-gate flash memory cell with a new program-disturbs immune array configuration;Fang;IEEE Trans Electron Devices,2014

2. Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell;Xu;Solid-State Electron,2019

3. A dual-bit split-gate EEPROM (DSG) cell in contactless array for single-Vcc high density flash memories;Ma;IEEE Int Electron Devices Meeting,1994

4. A novel high-density embedded AND-type split gate flash memory;Shen;Jpn J Appl Phys,2014

5. A dual-bit split-gate EEPROM (DSG) cell in contactless array for single-Vcc high density flash memories;Ma;Electron Devices Meeting,1994

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fabrication Process Improvement of Aggressively Scaled Dual-Bit/Cell Split-Gate Floating-Gate Flash Cell;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

2. Investigation of a New Disturb Effect in the Aggressively Scaled Dual-Bit/Cell Split-Gate Floating-Gate Flash Cell;2023 China Semiconductor Technology International Conference (CSTIC);2023-06-26

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