A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes-Reference-Cited by-同舟云学术

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A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

Published:2007-04 Issue:4 Volume:15 Page:483-488
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Wang Zhongfeng,Cui Zhiqiang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/4162500/04162517.pdf?arnumber=4162517

Cited by 33 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Type-2 QC LDPC codes and upper bounds on the minimum distance;AIP Conference Proceedings;2024

3. Check-Belief Propagation Decoding of LDPC Codes;IEEE Transactions on Communications;2023-12

4. HF-LDPC: HLS-friendly QC-LDPC FPGA Decoder with High Throughput and Flexibility;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06

5. A Low Complexity PEG-like Algorithm to Construct Quasi-Cyclic LDPC Codes;2023 12th International Symposium on Topics in Coding (ISTC);2023-09-04

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