HF-LDPC: HLS-friendly QC-LDPC FPGA Decoder with High Throughput and Flexibility-Reference-Cited by-同舟云学术

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HF-LDPC: HLS-friendly QC-LDPC FPGA Decoder with High Throughput and Flexibility

Published:2023-11-06 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 41st International Conference on Computer Design (ICCD)
language:
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Author:

Zhang Yifan¹,Cao Qiang¹,Wang Shaohua¹,Yao Jie²,Jiang Hong³

Affiliation:

1. Huazhong University of Science and Technology,Wuhan National Laboratory for Optoelectronics

2. Huazhong University of Science and Technology,School of Computer Science and Technology

3. University of Texas at Arlington,Department of Computer Science and Engineering

Funder

Research and Development

National Science Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10360938/10360940/10360987.pdf?arnumber=10360987

Reference22 articles.

1. Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation

2. LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms

3. A Survey and Evaluation of FPGA High-Level Synthesis Tools

4. MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows

5. ThunderGP

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