A 0.1–1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC-Reference-Cited by-同舟云学术

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A 0.1–1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC

Published:2019-08 Issue:8 Volume:29 Page:548-550
ISSN:1531-1309
Container-title:IEEE Microwave and Wireless Components Letters
language:
Short-container-title:IEEE Microw. Wireless Compon. Lett.

Author:

Park Suneui,Kim Juyeop^ORCID,Hwang Chanwoong,Park Hangi^ORCID,Yoo Seyeon^ORCID,Seong Taeho^ORCID,Choi Jaehyouk^ORCID

Funder

Ministry of Science and ICT, Korea, through the ITRC Support Program supervised by IITP

KIAT

Korea Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics

Link

http://xplorestaging.ieee.org/ielx7/7260/8790637/08744239.pdf?arnumber=8744239

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Analog Delay-Locked Loop with Digital Coarse Lock Incorporating Error Compensation for Fast and Robust Locking;Electronics;2024-06-27

2. A Radiation-Hardened Delay-Locked Loop Applied for Multiple Frequency Ranges;Journal of Circuits, Systems and Computers;2022-10-29

3. Analysis and Design of a Delay-Locked Loop with Multiple Radiation-hardened Techniques;Circuits, Systems, and Signal Processing;2022-08-19

4. A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL;Electronics;2022-08-04

5. A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2022-02

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