Process-variation Effects on 3D TLC Flash Reliability: Characterization and Mitigation Scheme
Author:
Funder
National Natural Science Foundation of China
Research and Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9282732/9282275/09282799.pdf?arnumber=9282799
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1. Random Flip Bit Aware Reading for Improving High-Density 3-D NAND Flash Performance;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-05
2. RiF: Improving Read Performance of Modern SSDs Using an On-Die Early-Retry Engine;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02
3. Are Superpages Super-fast? Distilling Flash Blocks to Unify Flash Pages of a Superpage in an SSD;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02
4. Lightweight Read Reference Voltage Calibration Strategy for Improving 3-D TLC NAND Flash Memory Reliability;IEEE Transactions on Device and Materials Reliability;2023-09
5. Improving the Endurance of Next Generation SSD’s using WOM-v Codes;ACM Transactions on Storage;2022-11-30
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