Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs-Reference-Cited by-同舟云学术

Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs

Published:2022-10-03 Issue: Volume: Page:
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Container-title:2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT)
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Author:

Vanaraj Anantharaj Thalaimalai¹,Sekar K Raja²,R Marshal³,G Lakshminarayanan⁴

Affiliation:

1. Research and Development, Western Digital Technologies Inc,Milpitas,California,USA

2. Centre for Development of Advanced Computing (CDAC),Bangalore,India

3. Ministry of Electronics and Information Technology,Indian Computer Emergency Response Team (CERT-In),New Delhi,India

4. National Institute of Technology Tiruchirappalli,Department of ECE,Tamil Nadu,India

Publisher

IEEE

Link

Reference16 articles.

1. SystemVerliog Standarad,0

4. Logic Verification and Simulation of FSM networks;hasan;Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium,0

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