High-performance and low parasitic capacitance CNT MOSFET: 1.2 mA/μm at V<sub>DS</sub> of 0.75 V by self-aligned doping in sub-20 nm spacer-Reference-Cited by-同舟云学术

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High-performance and low parasitic capacitance CNT MOSFET: 1.2 mA/μm at V_DS of 0.75 V by self-aligned doping in sub-20 nm spacer

Published:2023-12-09 Issue: Volume: Page:
ISSN:
Container-title:2023 International Electron Devices Meeting (IEDM)
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Author:

Li Shengman¹,Chao Tzu-Ang²,Gilardi Carlo¹,Safron Nathaniel³,Su Sheng-Kai²,Zeevi Gilad¹,Bechdolt Andrew Denis¹,Passlack Matthias³,Oberoi Aaryan³,Lin Qing¹,Zhang Ziehen⁴,Wang Kesong⁴,Kashyap Harshil⁴,Liew San-Lin²,Hou Vincent D.-H²,Kummel Andrew⁴,Radu Luliana²,Pitner Gregory³,Wong H.-S. Philip¹,Mitra Subhasish¹

Affiliation:

1. Stanford University,Stanford,CA,USA

2. TSMC,Hsinchu,Taiwan

3. TSMC,San Jose,USA

4. University of California,San Diego,CA,USA

Funder

National Science Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10413659/10413660/10413827.pdf?arnumber=10413827

Reference15 articles.

1. Carbon nanotube transistors: Making electronics from molecules

2. Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

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1. Nonideality in Arrayed Carbon Nanotube Field Effect Transistors Revealed by High-Resolution Transmission Electron Microscopy;ACS Nano;2024-08-07

2. Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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