FPGA Implementation of Arbiter PUFs for ideal Cryptographic Key Generation-Reference-Cited by-同舟云学术

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FPGA Implementation of Arbiter PUFs for ideal Cryptographic Key Generation

Published:2021-12-02 Issue: Volume: Page:
ISSN:
Container-title:2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA)
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Author:

Anitha Komma,Kumar Gopathoti Kiran,Rajeswari J,Majji Sankararao,Radhika Patnala Tulasi,Sri Sai Satyanarayana Damaraju

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9675837/9675843/09676119.pdf?arnumber=9676119

Reference16 articles.

1. Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks

2. Blur Gate Based Data Leakage Reduction Technique;ammupriya;ICON (Integrating Concepts),2019

3. Challenge-Response Pair (CRP) Generator Using Schmitt Trigger Physical Unclonable Function

4. A highly efficient and secure hardware implementation of the advanced encryption standard

5. A Novel Image Encryption Scheme Based on Self-Synchronous Chaotic Stream Cipher and Wavelet Transform

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1. Medical Robot Docking System;2022 4th International Conference on Inventive Research in Computing Applications (ICIRCA);2022-09-21

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