Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks-Reference-Cited by-同舟云学术

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Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks

Published:2019-05 Issue:5 Volume:27 Page:1080-1092
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

De Partha^ORCID,Mandal Chittaranjan^ORCID,Prampalli Udaya^ORCID

Funder

Australian Research Council

University of Melbournes 2014 International Research and Research Training Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8698469/08651372.pdf?arnumber=8651372

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