Low-Frequency Noise and Border Traps in Irradiated nMOS and pMOS Bulk Si FinFETs With SiO2/HfO2 Gate Dielectrics
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Vanderbilt University, Nashville, TN, USA
2. imec, Leuven, Belgium
Funder
Department of the Defense Threat Reduction Agency through its Basic Research Program
Air Force Office of Scientific Research
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Nuclear Energy and Engineering,Nuclear and High Energy Physics
Link
http://xplorestaging.ieee.org/ielx7/23/10103954/10025768.pdf?arnumber=10025768
Reference47 articles.
1. Reconciliation of different gate-voltage dependencies of 1/f noise in n-MOS and p-MOS transistors
2. Effects of oxide traps, interface traps, and ‘‘border traps’’ on metal‐oxide‐semiconductor devices
3. Improved Analysis of Low Frequency Noise in Field-Effect MOS Transistors
4. Geometry Dependence of Total-Dose Effects in Bulk FinFETs
5. Impacts of Through-Silicon Vias on Total-Ionizing-Dose Effects and Low-Frequency Noise in FinFETs
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1. Novel layout technique for single-event transient mitigation by the groove structure;Radiation Effects and Defects in Solids;2024-07-10
2. Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis;IEEE Transactions on Electron Devices;2024-03
3. Low-frequency noise in nanowires;Nanoscale;2023
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