Design and realization of high-performance wave-pipelined 8/spl times/8 b multiplier in CMOS technology
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx4/92/8376/00365452.pdf?arnumber=365452
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Benchmarking of DPL-based 8b × 8b novel wave-pipelined multiplier;International Journal of Electronics Letters;2016-04-21
2. A new wave-pipelining methodology: wave component sampling method;International Journal of Electronics;2013-06-08
3. Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier;IET Circuits, Devices & Systems;2013-05
4. Optimization techniques for FPGA-based wave-pipelined DSP blocks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-07
5. New Current-Mode Wave-Pipelined Architectures for High-Speed Analog-to-Digital Converters;IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications;2004-01
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