Compact model for vertical silicon nanowire based device simulation and circuit design-Reference-Cited by-同舟云学术

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Compact model for vertical silicon nanowire based device simulation and circuit design

Published:2015-11 Issue: Volume: Page:
ISSN:
Container-title:2015 International SoC Design Conference (ISOCC)
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Author:

Sharma M.,Maheshwaram S.,Prakash Om.,Bulusu A.,Saxena A. K.,Manhas S. K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7394793/7401627/07401675.pdf?arnumber=7401675

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study on self-heating effect and lifetime in vertical-channel field effect transistor;Microelectronics Reliability;2021-04

2. Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing ${I}_{OFF}$ in Various Sub-10-nm 3-D Transistors;IEEE Transactions on Electron Devices;2019-01

3. Nanoarrays for Systolic Biosequence Analysis;Journal of Circuits, Systems and Computers;2018-06-22

4. Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM;Solid-State Electronics;2018-02

5. Performance and Variability Analysis of SiNW 6T-SRAM Cell Using Compact Model With Parasitics;IEEE Transactions on Nanotechnology;2017-11

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