High Throughput, low cost, Fully Pipelined Architecture for AES Crypto Chip-Reference-Cited by-同舟云学术

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High Throughput, low cost, Fully Pipelined Architecture for AES Crypto Chip

Published:2006-09 Issue: Volume: Page:
ISSN:
Container-title:2006 Annual IEEE India Conference
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Author:

Iyer Nalini,Anandmohan P.V.,Poornaiah D.V,Kulkarni V.D.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4086217/4086218/04086285.pdf?arnumber=4086285

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High Throughput Pipelined Architecture for AES Cipher;Lecture Notes in Electrical Engineering;2021

2. Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture;Concurrency and Computation: Practice and Experience;2019-04-23

3. High Throughput AES Algorithm Using Parallel Subbytes and MixColumn;Wireless Personal Communications;2016-11-04

4. PSP CO2: An Efficient Hardware Architecture for AES Algorithm for High Throughput;Wireless Personal Communications;2015-05-17

5. PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC;Open Computer Science;2013-01-01

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