A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP-Reference-Cited by-同舟云学术

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A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP

Published:2021-09-13 Issue: Volume: Page:
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Container-title:ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
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Author:

Wong M. M.,Shrestha S. B.,Nambiar V. P.,Mani A.,Lee Y. K.,Koh E. K.,Jiang W.,Chai K. T. C.,Do A. T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9567713/9567736/09567782.pdf?arnumber=9567782

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth;IEEE Transactions on Biomedical Circuits and Systems;2023-12

2. 1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

4. Introduction;Neuromorphic Solutions for Sensor Fusion and Continual Learning Systems;2012-02-24

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