1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing-Reference-Cited by-同舟云学术

1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Wang B.¹,Wong M. M.²,Li D.¹,Chong Y. S.²,Zhou J.³,Wong W. F.³,Peh L.³,Mani A.²,Upadhyay M.³,Balaji A.³,Do A. T.²

Affiliation:

1. Singapore University of Technology and Design (SUTD)

2. Institute of Microelectronics (IME), Agency for Science, Technology and Research

3. National University of Singapore (NUS),Department of Computer Science,Singapore

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181759.pdf?arnumber=10181759

Reference9 articles.

1. Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip;wang;2020 Design Automation & Test in Europe Conference & Exhibition (DATE),0

2. A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS

3. AI-on-skin: Enabling On-body AI Inference for Wearable Artificial Skin Interfaces

4. 7.6 a 65nm 236.5 nJ/Classification neuromorphic processor with 7.5% energy overhead on-chip learning using direct spike-only feedback;park;2019 IEEE International Solid- State Circuits Conference - (ISSCC),0

5. A 2.1 pJ/SOP 40nm snn accelerator featuring on-chip transfer learning using Delta STDP;wong;ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC),0

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