A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET
Author:
Affiliation:
1. Samsuug Electronics,Hwaseong,Korea
2. Samsung Electronics,San Jose,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911419.pdf?arnumber=9911419
Reference5 articles.
1. A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS
2. 30.4 A 32Gb/s 2.9pJ/b Transceiver for Sequence-Coded PAM-4 Signalling with 4-to-6dB SNR Gain in 28nm FDSOI CMOS
3. A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM-4 SerDes in 65-nm CMOS;roshan-zamir;JSSC,2017
4. An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS
5. 21.6 A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS
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