Author:
Mishra Aparna,Grover Anuj
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Enhancing Low-Power SRAM Performance with FinFET Integration: A 10T Model Analysis;2024 International Conference on Communication, Computer Sciences and Engineering (IC3SE);2024-05-09
2. Voltage Boosted Schmitt Trigger Sense Amplifier (VBSTSA) With Improved Offset And Reaction Time For High Speed SRAMs;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01
3. Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM;2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2022-11-11
4. 3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
5. Design Of High Density Memory Cell Library For Low Voltage Operation In 65nm LSTP Technology;2021 IEEE 18th India Council International Conference (INDICON);2021-12-19