Design Of High Density Memory Cell Library For Low Voltage Operation In 65nm LSTP Technology-Reference-Cited by-同舟云学术

Design Of High Density Memory Cell Library For Low Voltage Operation In 65nm LSTP Technology

Published:2021-12-19 Issue: Volume: Page:
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Container-title:2021 IEEE 18th India Council International Conference (INDICON)
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Author:

Saxena Akshat¹,Bansal Swapnil¹,Sharma Divisha¹,Kumari Payal¹,Singh Sandeep Kumar¹,Kapil Priya¹,Iqbal Belal¹,Grover Anuj¹

Affiliation:

1. IIIT Delhi,Dept. Of Electronics and Communication,New Delhi,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9691480/9691481/09691642.pdf?arnumber=9691642

Reference15 articles.

1. Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques

2. Design of 6T, 5T and 4T SRAM Cell on Various Performance Metrics;wazir singh;2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom),2015

3. A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

4. A low leakage 9t sram cell for ultra-low power operation

5. Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance

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