Author:
Hellebrand S.,Reeb B.,Tarnick S.,Wunderlich H.-J.
Cited by
32 articles.
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2. A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs;IEEE Access;2021
3. Logic BIST With Capture-Per-Clock Hybrid Test Points;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-06
4. GDRIU Digital Section Implementation Using FPGA;2017 International Conference on Recent Advances in Electronics and Communication Technology (ICRAECT);2017-03
5. On the Generation of Compact Deterministic Test Sets for BIST Ready Designs;2013 22nd Asian Test Symposium;2013-11