Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability-Reference-Cited by-同舟云学术

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Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Published: Issue: Volume: Page:
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Container-title:ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.
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Author:

Tsukamoto Y.,Nii K.,Imaoka S.,Oda Y.,Ohbayashi S.,Yoshizawa T.,Makino H.,Ishibashi K.,Shinohara H.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/10431/33130/01560101.pdf?arnumber=1560101

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2. A Practical Design-Space Analysis of Compute-in-Memory With SRAM;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-04

3. An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2021-11-01

4. Performance analysis and yield estimation for a negative capacitance field effect transistor-based eight-transistor static random access memory;Semiconductor Science and Technology;2021-08-18

5. Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor;IEEE Journal of the Electron Devices Society;2020

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