1. Integration of Shift-Left Updates into Logic Synthesis and Macro Placement;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17
2. Delay-Driven Physically-Aware Logic Synthesis with Informed Search;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06
3. On the Interconnection Complexity vs Size Trade-off in Circuit Graphs;Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding;2023-11-02
4. Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30
5. CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks;2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC);2019-10