Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration-Reference-Cited by-同舟云学术

Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration

Published:2022-10-30 Issue: Volume: Page:
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Container-title:Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
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Author:

Zhou Xinyi¹,Ye Junjie²,Pui Chak-Wa²,Shao Kun³,Zhang Guangliang⁴,Wang Bin³,Hao Jianye⁵,Chen Guangyong⁶,Heng Pheng Ann¹

Affiliation:

1. The Chinese University of Hong Kong, Hong Kong, China

2. Huawei Noah's Ark Lab, Shenzhen, China

3. Huawei Noah's Ark Lab, Beijing, China

4. HiSilicon, Shenzhen, China

5. Huawei Noah's Ark Lab, Beijing, China and Tianjin University, Tianjin, China

6. Zhejiang Lab, Hangzhou, China

Funder

Hong Kong Innovation and Technology Fund Project

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3508352.3549361

Reference41 articles.

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3. M. Ebrahimi , F. Oboril , S. Kiamehr , and M. B. Tahoori , " Aging-aware logic synthesis," in 2013 IEEE/ACM International Conference on Computer-Aided Design , pp. 61 -- 68 , IEEE , 2013 . M. Ebrahimi, F. Oboril, S. Kiamehr, and M. B. Tahoori, "Aging-aware logic synthesis," in 2013 IEEE/ACM International Conference on Computer-Aided Design, pp. 61--68, IEEE, 2013.

4. K. O. Tinmaung , D. Howland , and R. Tessier , " Power-aware FPGA logic synthesis using binary decision diagrams," in Proceedings of the 15th International Symposium on Field Programmable Gate Arrays , pp. 148 -- 155 , 2007 . K. O. Tinmaung, D. Howland, and R. Tessier, "Power-aware FPGA logic synthesis using binary decision diagrams," in Proceedings of the 15th International Symposium on Field Programmable Gate Arrays, pp. 148--155, 2007.

5. Strongly NP-hard discrete gate-sizing problems

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