Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)-Reference-Cited by-同舟云学术

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Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)

Published:2017-11 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
language:
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Author:

Pui Chak-Wa,Chen Gengjie,Ma Yuzhe,Young Evangeline F. Y.,Yu Bei

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8167715/8203744/08203880.pdf?arnumber=8203880

Cited by 41 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Enabling Risk Management of Machine Learning Predictions for FPGA Routability;Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD;2024-09-09

2. OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

3. WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning;ACM Transactions on Design Automation of Electronic Systems;2024-05-03

4. Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02

5. An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs;Integration;2024-01

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