Author:
Izraelevitz Adam,Koenig Jack,Li Patrick,Lin Richard,Wang Angie,Magyar Albert,Kim Donggyu,Schmidt Colin,Markley Chick,Lawson Jim,Bachrach Jonathan
Cited by
114 articles.
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1. Accelerating Loop-Oriented RTL Simulation With Code Instrumentation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12
2. Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31
3. Fast, Robust and Transferable Prediction for Hardware Logic Synthesis;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28
4. Khronos: Fusing Memory Access for Improved Hardware RTL Simulation;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28
5. The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog;Proceedings of the ACM on Programming Languages;2023-10-16