Gate sizing and device technology selection algorithms for high-performance industrial designs

Author:

Ozdal Muhammet Mustafa,Burns Steven,Hu Jiang

Publisher

IEEE

Cited by 27 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-09

2. DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs;ACM Transactions on Design Automation of Electronic Systems;2022-12-16

3. VirtualSync+: Timing Optimization With Virtual Synchronization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12

4. ECO-GNN: Signoff Power Prediction using Graph Neural Networks with Subgraph Approximation;ACM Transactions on Design Automation of Electronic Systems;2022-10-27

5. A Graph Neural Network Method for Fast ECO Leakage Power Optimization;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17

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