Dynamic Comparator Design for High Speed ADCs
Author:
Affiliation:
1. Vardhaman College of Engineering, JNTUH,Communication Engineering,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9768398/9768400/09768408.pdf?arnumber=9768408
Reference8 articles.
1. Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology
2. A low-power low-offset dynamic comparator for analog to digital converters
3. A low-power high-resolution dynamic voltage comparator with input signal dependent power down technique
4. Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme
5. Investigation of MUX Using Various CMOS Circuit Style under Nanometer Technology;prabu;International Journal trend in Engineering and Research,2019
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1. Low Power High Speed Inverter Based Differential Input Dynamic Comparator;2024 16th International Conference on Electronics, Computers and Artificial Intelligence (ECAI);2024-06-27
2. Design of Voltage Comparator with High Voltage to Time Gain for ADC Applications;Lecture Notes in Networks and Systems;2024
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