Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs
Author:
Affiliation:
1. Indian Institute of Technology Kanpur,Kanpur,India
2. University of California Berkeley,California,USA
3. MaxLinear Inc.,Carlsbad,California,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10102927/10102928/10102942.pdf?arnumber=10102942
Reference7 articles.
1. Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs
2. 29.1 A 28nm Bulk-CMOS 4-to-8GHz ¡2mW Cryogenic Pulse Modulator for Scalable Quantum Computing
3. Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures
4. Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology
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1. Characterizing Analog Figure of Merits of 5 nm Technology Node FinFETs from 10 K to 400 K;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03
2. Modeling and Benchmarking 5nm Ferroelectric FinFET from Room Temperature down to Cryogenic Temperatures;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02
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