Ferroelectric FET Threshold Voltage Optimization for Reliable In-Memory Computing
Author:
Affiliation:
1. Karlsruhe Institute of Technology,Germany
2. Rochester Institute of Technology,USA
3. University of Stuttgart,Chair of Semiconductor Test and Reliability (STAR),Germany
Funder
Office of Naval Research
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764551.pdf?arnumber=9764551
Reference25 articles.
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4. Sentaurus device user guide, version p-2019.03-sp1.” fdsoi devices featuring 20nm gate length for 14nm node and beyond;IEEE IEDM 2013,2013
5. High performance utbb;liu,2009
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1. Oxygen Vacancy Control as a Strategy to Enhance Imprinting Effect in Hafnia Ferroelectric Devices;IEEE Transactions on Electron Devices;2023-01
2. Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs;IEEE Open Journal of Circuits and Systems;2023
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