Study of Avalanche Behavior in 3 kV GaN Vertical P-N Diode Under UIS Stress for Edge-termination Optimization-Reference-Cited by-同舟云学术

Study of Avalanche Behavior in 3 kV GaN Vertical P-N Diode Under UIS Stress for Edge-termination Optimization

Published:2022-03 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Reliability Physics Symposium (IRPS)
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Author:

Shankar Bhawani¹,Bian Zhengliang¹,Zeng Ke¹,Meng Chuanzhe¹,Martinez Rafael Perez¹,Chowdhury Srabanti¹,Gunning Brendan²,Flicker Jack²,Binder Andrew²,Dickerson Jeramy Ray²,Kaplar Robert²

Affiliation:

1. Stanford University,Electrical Engineering,Stanford,CA,USA,94305

2. Sandia National Labs,Albuquerque,NM,USA,87123

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764525.pdf?arnumber=9764525

Reference30 articles.

1. Literature Review of Spin On Glass

2. Reliability studies of vertical GaN devices based on bulk GaN substrates

3. On-Wafer Investigation of Avalanche Robustness in 1.3 kV GaN-on-GaN P-N Diode Under Unclamped Inductive Switching Stress

4. First Observations on the Trap-Induced Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs

5. 2.8 kV Avalanche in Vertical GaN PN Diode Utilizing Field Plate on Hydrogen Passivated P-Layer

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