Implementing latency-insensitive dataflow blocks

Author:

Cao Bingyi,Ross Kenneth A.,Kim Martha A.,Edwards Stephen A.

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Synthesized In-BramGarbage Collection for Accelerators with Immutable Memory;2022 32nd International Conference on Field-Programmable Logic and Applications (FPL);2022-08

2. Wire sorts: a language abstraction for safe hardware composition;Proceedings of the 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation;2021-06-18

3. Compositional Dataflow Circuits;ACM Transactions on Embedded Computing Systems;2019-01-31

4. Compositional dataflow circuits;Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design;2017-09-29

5. Deadlock-free joins in DB-mesh, an asynchronous systolic array accelerator;Proceedings of the 13th International Workshop on Data Management on New Hardware;2017-05-14

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