Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture-Reference-Cited by-同舟云学术

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Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture

Published:2022-03-16 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on Electronics and Renewable Systems (ICEARS)
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Author:

Nagarajan P.¹,Kumar N. Ashok²,Arockia Dhanraj Joshuva³,Kumar T. Senthil⁴,Sundari L Mohana⁵

Affiliation:

1. Rajalakshmi Institute of Technology,Department of CCE,Chennai,Tamilnadu,India

2. Sree Vidyanikethan Engineering College,Department of ECE,Andhra Pradhesh,India

3. Hindustan Institute of Technology and Science,Department of Mechanical Engineering,Padur, Chennai,Tamil Nadu,India

4. GRT Institute of Engineering and Technology,Department of ECE,Tiruttani,Tamilnadu,India

5. Saveetha Engineering College,Department of ECE,Chennai,Tamilnadu,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9751779/9751722/09752249.pdf?arnumber=9752249

Reference17 articles.

1. Efficient timing element design featuring low power vlsi application;nagarajan;International Journal of Engineering and Technology (IJET),2016

2. Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems

3. Interaction of Spatial Computing In Augmented Reality

4. An Intelligent Face Detection by Corner Detection using Special Morphological Masking System and Fast Algorithm

5. An Embarking User Friendly Palmprint Biometric Recognition System with Topnotch Security

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