Process variation study of Ground Plane SOI MOSFET
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5543927/5548154/05548155.pdf?arnumber=5548155
Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Influence of Process Variations on the Electrical Performance of SiC Power MOSFETs;IEEE Transactions on Electron Devices;2021-01
2. Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study;IEEE Access;2020
3. Design and Performance Analysis of Hybrid SELBOX Junctionless FinFET;Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials;2019-05-07
4. Comparative Investigation on Bias Dependent RF Performance of SOI Substrates;ECS Journal of Solid State Science and Technology;2019
5. Analytical modeling of InSb/AlInSb heterostructure dual gate high electron mobility transistors;AEU - International Journal of Electronics and Communications;2018-09
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