Design and Performance Analysis of Hybrid SELBOX Junctionless FinFET

Abstract

In this work, the performance of selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure is analysed using numerical simulations. The proposed structure exhibits better thermal resistance (RTH), which is the measure of the self-heating effect (SHE). The DC and analog performances of the proposed structure were studied and compared with the conventional and hybrid (or inverted-T) JLFinFETs (JLTs). The ION of the hybrid SELBOX- JLFinFET is 1.43x times better than the ION of the JLT due to the added advantage of different technologies, such as 2D-ultra-thin-body (UTB), 3D-FinFET, and SELBOX. The proposed device is modeled using sprocess and simulation study is carried using sdevice. Various analog parameters, such as transconductance (gm), transconductance generation factor (TGF = gm/IDS), unity current gain frequency (fT), early voltage (VEA), total gate capacitance (Cgg), and intrinsic gain (A0), are evaluated. The proposed device with a minimum feature size of 10nm exhibited better TGF, fT, VEA, and A0 in the deep-inversion region of operation.