Author:
Hayashi Tatsushi,Lin Po Yu,Watanabe Ryoichi,Ichikawa Seiko
Cited by
3 articles.
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1. Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023
2. Multi-Package Co-Design for Chiplet Integration;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30
3. Stress Analysis of Underfill in Advanced Semiconductor Package Structures;Journal of The Japan Institute of Electronics Packaging;2022-09-01