Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB)-Reference-Cited by-同舟云学术

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Design and Development of High Density Fan-Out Wafer Level Package (HD-FOWLP) for Deep Neural Network (DNN) Chiplet Accelerators using Advanced Interface Bus (AIB)

Published:2021-06 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
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Author:

Rotaru Mihai D.,Tang Wei,Rahul Dutta,Zhang Zhengya

Funder

Defense Advanced Research Projects Agency

Office of Naval Research

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9501397/9501403/09501635.pdf?arnumber=9501635

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Deep Reinforcement Learning-Based Power Distribution Network Design Optimization for Multi-Chiplet System;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Exploring Heterogeneous Integration: Its Essence and Future Path;Computer;2024-02

3. SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

4. Assembly process characterization of 3D Stacking of Heterogeneous Chiplets;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05

5. Exploiting signal skew to reduce delay uncertainty for chiplet interconnects;IEICE Electronics Express;2023-07-10

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