Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing-Reference-Cited by-同舟云学术

Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing

Published:2021-08-18 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Test Conference in Asia (ITC-Asia)
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Author:

Yan Aibin¹,Zhai Zijie¹,Wang Lele¹,Zhang Jixiang¹,Cui Ningning¹,Ni Tianming²,Wen Xiaoqing³

Affiliation:

1. Anhui University,School of Computer Science and Technology,Hefei,China

2. Anhui Polytechnic University,College of Electrical Engineering,Wuhu,China

3. Kyushu Institute of Technology,Graduate School of Computer Science and Systems Engineering,Fukuoka,Japan

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9808359/9808467/09808602.pdf?arnumber=9808602

Reference29 articles.

1. Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

2. Design of a Radiation Hardened Latch for Low-Power Circuits

3. Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation

4. Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations;rajaei;Journal of Circuits Systems and Computers,2014

5. DIRT latch: A novel low cost double node upset tolerant latch

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