Performance Analysis of Different SRAM Cells and Proposed 9T SRAM Cell

Author:

Ashwani J.1,Deepa K.1,Kumar K. Charan1,Karthick B.1,Kandasamy Nehru1

Affiliation:

1. Madanapalle Institute of Technology & Science,Andhra Pradesh,INDIA

Publisher

IEEE

Reference17 articles.

1. Design and comparative analysis of low power 64 Bit SRAM and its peripherals using power reduction techniques

2. Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

3. Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay;gavaskar;Journal of Ambient Intelligence and Humanized Computing,2021

4. Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm

5. Bit line and storage node decoupled 13T SRAM cell in 22-nm technology node;roy;Wulfenia Journal,2013

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Performance Analysis of CMOS SRAM 6T, 7T and 9T Cells using Cadence at 180nm Technology;2024 3rd International Conference for Innovation in Technology (INOCON);2024-03-01

2. Optimized Speed and Power Consumption in a 14T SRAM Bit Cell by Use of Shorted-Gate FinFET;2023 3rd International Conference on Advancement in Electronics & Communication Engineering (AECE);2023-11-23

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