Design and Implementation of Physical Unclonable Function in Field Programmable Gate Array
Author:
Affiliation:
1. Kongu Engineering College,Department of ECE,Erode,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10192571/10192589/10192681.pdf?arnumber=10192681
Reference15 articles.
1. FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures
2. Xilinx FPGA-based Ring Oscillator PUFs: Design Challenges and Solutions
3. A Low-Power Parallel Architecture for Linear Feedback Shift Registers;zhang;IEEE Transactions on Circuits and Systems II Express Briefs,2019
4. Design and Implementation of Linear Feedback shift Register based physical unclonable function;nagamalli;International Journal of Advanced Research in Computer and Communication Engineering,0
5. FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings
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